For device isolation, a local oxidation of silicon (LOCOS) process has been widely employed. The LOCOS process forms a device isolation structure by thermally oxidizing a silicon substrate itself using a nitride layer as a mask. Therefore, the LOCOS process achieves the simplicity of a fabrication process and provides an oxide layer having high quality and a high resistance against stresses.
However, the device isolation achieved by the LOCOS process has several shortcomings such as a bird's-beak, which may be formed at the edges of the device isolation structure. Therefore, the LOCOS process increases the area of the device isolation structure and has a difficulty in the miniaturization of a semiconductor device.
Accordingly, various methods to solve such problems in the conventional LOCOS process have been suggested. One method is to form a shallow trench isolation (STI) structure as the device isolation structure. Briefly, an STI structure formation process makes a trench in a silicon substrate and fills an insulating material into the trench. Thus, the STI structure with a small area and the miniaturization of the semiconductor device are achieved.
In detail, a conventional STI structure forming process is as follows. A trench is formed in a silicon substrate by a dry etch. Subsequently, an annealing process is performed to cure etching damages inside the trench. An oxide layer is then formed by thermally oxidizing the inside of the trench so as to enhance a surface characteristic and to prevent the occurrence of problems due to the rounded sidewalls of the STI structure. Subsequently, an insulating layer is deposited inside the trench and on the entire surface of the resulting structure. A Chemical Mechanical Polishing (CMP) is then performed to planarize the surface of the resulting structure and complete gate lines.
However, in the conventional STI formation process, several problems occur due to a difference in height between a field region and a moat region. For example, as shown at reference number 101 in FIG. 1, if the level of the field region 100 is lower than that of the moat region 200, leakage current may be generated due to polysilicon residue between the field region 100 and the moat region 200. In addition, polysilicon for gate electrodes may easily penetrate into a void 102 in the STI structure, thereby causing another leakage current.
On the other hand, if the level of the field region is higher than that of the moat region, several problems may be generated as well. For example, moat pits may arise in an exposed area during a later etching process for polysilicon. Moreover, if a contact pattern is inadequately aligned, some portion of an oxide layer may be lost, resulting in leakage fails. In addition, the difference in height between the field region 100 and the moat region 200 makes it difficult to control critical dimensions during later patterning and etching processes. Additionally, the edges of a gate electrode and the field region may be damaged by the plasma etching process for forming spacers and the ion implantation process for forming source and drain regions.